The present invention relates to the field of CMOS integrated circuit design, in particular to a voltage-controlled oscillator circuit and a phase-locked loop circuit.
In a phase-locked loop (PLL) design, a voltage-controlled oscillator (VCO) is one of the core modules. Taking a charge pump phase-locked loop (PLL) as an example, during working, a charge pump converts an output of a phase frequency detector into a pulse current, which is converted into a DC control voltage VC that serves as a voltage-controlled signal of the voltage-controlled oscillator after passing though a low pass filter. Therefore, for the voltage-controlled oscillator, the DC control voltage VC serves as an input thereof, a frequency serves as an output thereof, and an oscillation frequency thereof directly determines a frequency range in which the phase-locked loop PLL can work.
A ring oscillator consisting of multistage single-ended or differential inverters is a main common voltage-controlled oscillator, wherein an equivalent resistance or equivalent capacitance of output end of the inverter is changed by DC control voltage VC, so as to change an oscillation frequency of the ring oscillator.
A common voltage-controlled oscillator is shown in FIG. 1, which is a ring oscillator consisting of an odd number of inverters, wherein the ring oscillator is driven by a PMOS transistor controlled by a DC control voltage VC output by a filter. Different DC control voltage VC corresponding to different current capacities provided by the PMOS transistor for the ring oscillator, and thus different oscillation frequencies are output.
For the ring oscillator of such the structure, the DC control voltage VC is used in a range of 0V to VDD-Vgs, wherein VDD is the power supply at the source of the PMOS transistor, and Vgs is a gate-source voltage drop of the PMOS transistor. However, due to the effect of a process corner, etc., when SS corner and FF corner conditions are covered, the use range of the DC control voltage VC may be reduced dramatically. In the same working frequency range of the voltage-controlled oscillator, when the use range of the DC control voltage VC is larger, a gain of the voltage-controlled oscillator is smaller, causing a smaller jitter. Therefore, in order to reduce clock noise, it is necessary to increase the use range of the DC control voltage VC.